Apple Silicon Compiler Bring-up
Validated code generation and resolved ABI compatibility across the Swift/Clang toolchain for M1-class targets.
Endurance athletics teaches the same lessons as systems engineering: deliberate practice, measurable progress, and staying calm under pressure.
03 — Telemetry
Race Telemetry
Real GPS data from actual races

Full marathon
First marathon finish after four months of structured training.

Purple belt competitor
Multiple matches in a single day, adapting under stress.

Olympic distance
Open water swim, bike, and run.
02 — Execution
Validated code generation and resolved ABI compatibility across the Swift/Clang toolchain for M1-class targets.
Tuned vectorization cost models and codegen heuristics for RISC-V vector workloads, preventing backslides with strict regression coverage.
Flagship iOS client in Swift and multi-cloud ML deployment for real-time generative AI interior design.
Implemented MaskFormer, DPT-Large, and YOLOS-small TTNN models for Tenstorrent hardware acceleration.
Open source artifacts and deep-tech products. Real systems engineering requires receipts.
04 — Open Source
Live Product
Multi-agent CLI orchestrating bug-finding, refutation, and consensus to produce pristine code reviews.
Orchestrating an adversarial multi-agent system (proposer vs. verifier) to mathematically eliminate LLM hallucinations in code review. It forces agents to prove bugs with evidence before reporting, shifting AI from a noisy text generator to a deterministic verification engine.
Apple / Swift Compiler
Implemented getter/setter interoperability directly within the official Swift compiler. (PR #40842)
Bridging two notoriously complex ASTs and type systems to achieve zero-cost abstractions requires an incredibly deep knowledge of compiler architecture, memory models, and ABI compatibility. The code ships to millions of developers using Xcode and the Swift toolchain.
Tenstorrent / tt-metal
End-to-end execution of MaskFormer (PR #32335), DPT-Large (PR #33123), and YOLOS-small (PR #32500).
Mapping complex neural network operations to novel, non-GPU spatial architectures. Bringing up a hybrid Swin-B decoder requires intimate understanding of low-level memory routing and writing custom hardware-specific kernels to extract bare-metal performance.